Generally, a physical connection between a chip of a power semiconductor and a chip carrier is implemented in a manner of gold-silicon eutectic welding. A specific implementation process is: as shown in FIG. 1 and FIG. 2, a gold layer is first electroplated on surfaces of a metal-material chip carrier 21; a chip 23 with a silicon substrate is then rubbed in a welding region 22 on the chip carrier 21 at a temperature above a gold-silicon eutectic temperature (363 degrees Celsius (° C.)); a liquid gold-silicon alloy is formed after gold-silicon reaction; and a gold-silicon alloy layer 24 formed after the liquid gold-silicon alloy is cooled implements a physical connection between the chip 23 and the chip carrier 21.
However, in order to achieve a proper connection between the chip and the chip carrier, it is generally required that the gold layer plated on the chip carrier be at least 2.5 microns in thickness. Further, as is limited by electroplating techniques, the chip carrier usually can only be plated with gold as a whole. That is, all outer surfaces (including a top surface 211, a side surface 212, and a bottom surface 213, which are shown in FIG. 2) of the chip carrier are plated with gold simultaneously. For current electroplating techniques, it is hard to plate only one surface of the chip carrier with gold, or plate the welding region 22 partially with gold. However, an area of the welding region only accounts for a few percent of an area of all the outer surfaces of the chip carrier, and a gold plating cost is calculated based on a gold plating area (a sum of areas of six surfaces of a cube), and therefore a cost of the chip carrier is high. In addition, as the gold price keeps rising, the cost of the chip carrier will also keep rising. Therefore, a cost of applying gold-silicon eutectic welding to power electronic products will be higher and higher.
Therefore, it is necessary for those skilled in the art to provide a welding method, which further reduces the cost of gold-silicon eutectic welding on the premise of ensuring a proper connection between a chip and a chip carrier.